The present invention relates generally to non-volatile memory integrated circuit devices, and more specifically to increasing the speed of programming such devices.
Non-volatile memory devices are used in the semiconductor integrated circuit industry in logic systems, such as microprocessors, and are used for creating storage elements such as memory boards or solid state hard disks. A conventional non-volatile or flash memory device includes a plurality of memory cells typically organized in the plurality of memory sectors. Within each memory sector, the memory cells are arranged in a array comprising a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the respective rows of the memory cells, and a plurality of bit lines are coupled to the respective columns of the memory cells. Each memory cell is capable of storing one bit. During the operation of a conventional non-volatile memory, a memory cell is programmed by supplying a current from a high voltage power supply to the drain of the memory cell through the respective bit lines to which the memory cells are connected when the non-volatile memory is in a conventional embedded program mode.
With the advent of low and very low voltage flash non-volatile memories, operated at or below 2.7 V, the die area occupied by the on-chip voltage multiplier charge pump becomes prohibitively large. The reason for this increase in the size of the charge pump is explained below.
The open circuit voltage VMO of a n-stage charge pump is approximately given by formula (1)
VMO=n(VDDxe2x88x92VTH)xe2x80x83xe2x80x83(1)
where
n=numbers of stages
VDD=power supply voltage
VTH=average threshold voltage for NMOS transistors in the charge pump chain.
With reference to FIG. 4, a state-of-the-art charge pump 20 is shown. The internal charge pump 20 receives a low voltage power supply VDD at an input terminal 22 and produces a programming voltage VM at an output terminal 24. A plurality of diode-connected NMOS transistors 215 are connected in series between the input terminal 22 and the output terminal 24. Between each of the diode transistors 215 is a node 230. A clock signal CLK is supplied to a clock input 28 and is inverted by an inverter 223 to provide an inverted clock signal {overscore (CLK)} 221. The inverted clock signal 221 is inverted again by a second inverter 225 to provide a clock signal 212. Capacitors 219 are connected between each of the nodes 230 and one of the clock signals 212, 221. Alternating nodes (N1, N3, N5) are connected to the clock signal line 212 through one of the capacitors 219, while the other nodes (N2, N4, N6) are connected through a capacitor 219 to the inverted clock signal line 221.
In FIG. 4, the internal nodes 230 are labeled Nk, k=1, 2 . . . 6. The average voltage at node Nk is
{tilde over (V)}k=k(VDDxe2x88x92{tilde over (V)}THk)xe2x80x83xe2x80x83(2)
The average threshold voltage {tilde over (V)}THk of the NMOS transistor at node Nk is affected by the substrate bias provided by the average node voltage {tilde over (V)}k. Formula (3) provides an approximation of the substrate bias effect on increasing {tilde over (V)}THk:
{tilde over (V)}THk=VTHo+xcex3({square root over ({tilde over (V)})}k+xcfx86Bxe2x88x92{square root over (xcfx86B)})xe2x80x83xe2x80x83(3)
Where {tilde over (V)}THo is the threshold voltage at zero substrate bias, xcex3 is the substrate bias coefficient and xcfx86B is the built in substrate (bulk) voltage. Typical values are:
VTHoxe2x89xa10 for NMOS native transistors (No enhancement implant)
xcex3xe2x89xa10.1÷0.9{square root over (V)}
xcfx86Bxe2x89xa10.6÷0.7V
A trial and error iterative computation for VMO and {tilde over (V)}TH in formula (1) yields a typical value of {tilde over (V)}TH=1.5V for n=8÷10 stages. With reference to FIG. 5, the open circuit voltage VMO 515 of the charge pump is plotted with respect to the power supply voltage VDD 519. Under load, VM has the approximate behavior:                                           V            ~                    M                =                                            V              ~                        MO                    -                      n            ⁢                                          T                C                            ·                                                I                  ~                                LOAD                                                                        (        4        )            
where T=clock period, C=capacitor value. Assuming that {tilde over (V)}Mnominal should be {tilde over (V)}Mnominal=10V as imposed by the hot electron injection mechanism, the current capability of the charge pump is:                                           I                                          LOAD                max                            ⁢                              xe2x80x83                                              =                                                                      V                  ~                                Mo                            -                                                V                  ~                                                  M                  nominal                                                                    n              ⁢                              T                C                                                    ⁢                  xe2x80x83                                    (        5        )            
provided that {tilde over (V)}Mo greater than {tilde over (V)}Mnominl. From FIG. 5, it can be seen from the graph 525 that the current capability 515 decreases dramatically for lower values of VDD 519.
Moreover, if one assumes that the programming cell current (Flash hot electron injection mechanism) is IPRG CELLxe2x89xa1200 xcexcA., then the number of bits (q), i.e. memory cells, which can be simultaneously programmed is:                     q        =                                            I                                                LOAD                  max                                ⁢                                  xe2x80x83                                                                    I                              PRG                ⁢                                  xe2x80x83                                ⁢                CELL                                              =                                                                      V                  ~                                Mo                            -                                                V                  ~                                                  M                  nominal                                                                    n              ·                              T                C                            ·                              I                                                      PRG                    ⁢                                          xe2x80x83                                        ⁢                    CELL                                    ⁢                                      xe2x80x83                                                                                                          (        6        )                                q        =                                            n              ⁡                              (                                                      V                    DD                                    -                                                            V                      ~                                        TH                                                  )                                      -                          V                              M                nominal                                                          n            ·                          T              C                        ·                          I                              PRG                ⁢                                  xe2x80x83                                ⁢                CELL                                                                        (        7        )                                q        =                              ·                          C              T                                ·                                                    n                ⁡                                  (                                                            V                      DD                                        -                                                                  V                        ~                                            TH                                                        )                                            -                              V                                  M                  nominal                                                                    I                              PRG                ⁢                                  xe2x80x83                                ⁢                CELL                                                                        (        8        )            
Assuming that C=100 pF and T=100 ns, and using Equation (8) with the other numerical values assumed above, the following results are obtained:
n=10
{tilde over (V)}TH=1.5V
VMnominal=10V
IPREG CELL=200 xcexcA
C=100 pF
T=100 ns
xe2x80x83q=[5(VDDxe2x88x922.5)]bits(with VDD in volts)xe2x80x83xe2x80x83(9)
Table 1 shows, in a second column, the number of bits that can be programmed at one time when the capacitance is 100 pF, based on various values of the power supply voltage VDD, shown in the first column. The third column of Table 1 shows the corresponding capacitance value when the programming rate is fixed at eight bits at a time for each of the power supply voltage VDD values of the first column.
The following results can be observed from Table 1. At VDD=3V, one can either have C=100 pF and write only 2 bits at a time or, one can have C=320 pF and write 8 bits at a time. For comparison, at VDD=4.5V, one can either have C=100 pF and write 10 bits at a time or have C=80 pF and write 8 bits at a time. Therefore, to be able to write 8 bits at a time, and to reduce the internal voltage from VDD=4.5V down to VDD=3V, the area of the charge pump capacitors has to be increased by 400%       (                  320        ⁢                  xe2x80x83                ⁢        pF                    80        ⁢                  xe2x80x83                ⁢        pF              )    ,
which is prohibitively large.
Attempts have been made in the prior art to increase the speed of programming flash non-volatile memories. U.S. Pat. No. 5,663,918 to Javanifard et al. discloses an integrated circuit having internal power supplies including circuitry for selecting either the external supply voltages or the internal power supplies to supply voltages to the remaining circuitry of the integrated circuit. The integrated circuit comprises voltage detector circuits for detecting the external voltage levels and a control circuit for selecting either the external supply voltages or the internal power supplies in response to the detected external voltages. The patent describes the mutually exclusive use of the external power supply and the operating supply voltage driven from the internal charge pump. Additionally, the regulation method is based upon the control of the frequency of the charge pump by means of a voltage control oscillator.
U.S. Pat. No. 6,014,332 to Roohparvar discloses a flash memory which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming.
It is the object of the present invention to provide a dual mode power supply for speeding up the programming of flash nonvolatile memories without having to increase the charge pump size when the flash memories are operated with low voltage power supplies.
It is a further object of the present invention to provide a dual mode high voltage power supply that has a first mode that programs using only the internal charge pump driven from the low voltage power supply VDD and a second mode that programs using the internal charge pump in conjunction with an external high voltage power supply in order to program a larger amount of memory cells simultaneously.
The above objects have been achieved by a dual mode high voltage power supply circuit having an external high voltage switch which determines whether the memory blocks of a nonvolatile memory circuit are programmed by an internal high voltage produced by an internal charge pump or are programmed by an external power supply high voltage in conjunction with the internal charge pump high voltage. When the dual mode power supply circuit is operating only on its internal charge pump high voltage, in order to keep the die area small, only one or two bits would be programmed at the same time. This is a first mode of operation. However, when the external power supply high voltage is available, eight or more bits can be written to at the same time, thus the throughput is four or more times larger. This is a second mode of operation. The switching from slow to fast programming mode can be dictated by a command or can be automatically executed by the flash memory itself based upon sensing the external voltage.
The dual mode power supply circuit includes the use of hysteresis comparator as a means of regulating the programming voltage by turning on or off the constant frequency clocks feeding the internal charge pump and additionally in the fast programming mode by turning on or off the external voltage switch. (The second power voltage is external but the switch controlling its distribution is internal.) This feedback loop built by the means of the hysteresis comparator allows the programming voltage from the internal charge pump to be matched by the external power supply as this programming voltage value is very critical for the overall performance of the non-volatile memory cells (both data retention and cell endurance).